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STGIPS14K60
IGBT intelligent power module (IPM) 12 A, 600 V, DBC isolated, SDIP-25L molded
Features
12 A, 600 V 3-phase IGBT inverter bridge including control ICs for gate driving and freewheeling diodes 3.3 V, 5 V, 15 V CMOS/TTL inputs comparators with hysteresis and pull down / pull up resistors Internal bootstrap diode Interlocking function VCE(sat) negative temperature coefficient Short-circuit rugged IGBTs Undervoltage lockout Smart shutdown function Comparator for fault protection against over temperature and overcurrent DBC fully isolated package Isolation rating of 2500 Vrms/min
SDIP-25L

technology. Please refer to dedicated technical note TN0107 for mounting instructions.
Applications

3-phase inverters for motor drives Home appliances, such as washing machines, refrigerators, air conditioners
Description
The STGIPS14K60 intelligent power module provides a compact, high performance AC motor drive for a simple and rugged design. It mainly targets low power inverters for applications such as home appliances and air conditioners. It combines ST proprietary control ICs with the most advanced short circuit rugged IGBT system Table 1. Device summary
Marking GIPS14K60 Package SDIP-25L Packaging Tube
Order code STGIPS14K60
June 2010
Doc ID 15927 Rev 3
1/19
www.st.com 19
Contents
STGIPS14K60
Contents
1 2 Internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 5
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Doc ID 15927 Rev 3
STGIPS14K60
Internal block diagram and pin configuration
1
Internal block diagram and pin configuration
Figure 1. Internal block diagram
Pin 1 OUT U VBOOT U
LIN Vboot
Pin 25 P
LIN-U HIN-U VCC
SD/OD HVG HIN VCC DT LVG CP+ GND OUT
U
NU
OUT V VBOOT V
LIN Vboot
P
GND LIN-V HIN-V
SD/OD HVG HIN VCC DT LVG CP+ GND OUT
V
NV
OUT W VBOOT W
LIN Vboot
P
LIN-W HIN-W SD/OD CIN Pin 16
SD/OD HVG HIN VCC DT LVG CP+ GND OUT
W
NW Pin 17
AM05002v1
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Internal block diagram and pin configuration Table 2.
Pin n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
STGIPS14K60
Pin description
Symbol OUTU Vboot U LINU HINU VCC OUTV Vboot V GND LINV HINV OUTW Vboot W LINW HINW SD / OD CIN NW W P NV V P NU U P Description High side reference output for U phase Bootstrap voltage for U phase Low side logic input for U phase High side logic input for U phase Low voltage power supply High side reference output for V phase Bootstrap voltage for V phase Ground Low side logic input for V phase High side logic input for V phase High side reference output for W phase Bootstrap voltage for W phase Low side logic input for W phase High side logic input for W phase Shut down logic input (active low) / open drain (comparator output) Comparator input Negative DC input for W phase W phase output Positive DC input Negative DC input for V phase V phase output Positive DC input Negative DC input for U phase U phase output Positive DC input
Figure 2.
Pin layout (bottom view)
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STGIPS14K60
Electrical ratings
2
2.1
Electrical ratings
Absolute maximum ratings
Table 3.
Symbol VPN VPN(surge) VCES IC(2) ICP (3) PTOT tscw
Inverter part
Parameter Supply voltage applied between P - NU, NV, NW Supply voltage (surge) applied between P - NU, NV, NW Collector emitter voltage (VIN(1) = 0) Each IGBT continuous collector current at TC = 25C Each IGBT pulsed collector current Each IGBT total dissipation at TC = 25C Short circuit withstand time, VCE = 0.5 V(BR)CES TJ = 125 C, VCC = Vboot= 15 V, VIN (1)= 0 / 5 V Value 450 500 600 12 30 33 5 Unit V V V A A W s
1. Applied between HINi, LINi and GND for i = U, V, W 2. Calculated according to the iterative formula:
T j ( max ) - T C I C ( T C ) = --------------------------------------------------------------------------------------------------------R thj - c x V CE ( sat ) ( max ) ( T j ( max ), I C ( T C ) )
3. Pulse width limited by max junction temperature
Table 4.
Symbol VOUT VCC VCIN Vboot VIN VSD/OD dVOUT/dt
Control part
Parameter Output voltage applied between OUTU, OUTV, OUTW - GND Low voltage power supply Comparator input voltage Bootstrap voltage applied between Vboot i - OUTi for i = U, V, W Logic input voltage applied between HIN, LIN and GND Open drain voltage Allowed output slew rate Value Vboot - 21 to Vboot + 0.3 -0.3 to +21 -0.3 to VCC +0.3 -0.3 to 620 -0.3 to 15 -0.3 to 15 50 Unit V V V V V V V/ns
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Electrical ratings Table 5.
Symbol VISO TJ
STGIPS14K60 Total system
Parameter Isolation withstand voltage applied between each pin and heatsink plate (AC voltage, t = 60 sec.) Operating junction temperature Value 2500 -40 to 125 Unit V C
Table 6.
Symbol RthJC
Thermal data
Parameter Thermal resistance junction-case single IGBT Thermal resistance junction-case single diode Value 3 5.5 Unit C/W C/W
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STGIPS14K60
Electrical characteristics
3
Electrical characteristics
(TJ = 25 C unless otherwise specified).
Table 7.
Symbol
Inverter part
Value Parameter Test conditions Min. VCC = Vboot = 15 V, VIN(1)= 0 / 5 V, IC = 7 A VCC = Vboot = 15 V, VIN(1)= 0 / 5 V, IC = 7 A, TJ = 125 C VCE = 600 V, VCC = VBoot = 15 V VIN(1) = 0 "logic state", IC = 7 A Typ. 2.1 1.8 100 2.1 A V Max. 2.5 V Unit
VCE(sat)
Collector-emitter saturation voltage
ICES VF
Collector-cut off current (VIN(1)= 0 "logic state") Diode forward voltage
Inductive load switching time and energy ton tc(on) toff tc(off) trr Eon Eoff Turn-on time Crossover time (on) Turn-off time Crossover time (off) Reverse recovery time Turn-on switching losses Turn-off switching losses VDD = 300 V, VCC = Vboot = 15 V, VIN(1) = 0 / 5 V, IC = 7 A (see Figure 5) 270 130 320 110 130 150 J 90 ns
1. Applied between HINi, LINi and GND for i = U, V, W (LIN inputs are active-low).
Note:
tON and tOFF include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the switching time of IGBT itself under the internally given gate driving condition.
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Electrical characteristics Figure 3. Switching time test circuit
STGIPS14K60
Figure 4.
Switching time definition
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Electrical characteristics
3.1
Table 8.
Symbol Vcc_hys Vcc_thON Vcc_thOFF Iqccu
Control part
Low voltage power supply
Parameter Vcc UV hysteresis Vcc UV turn ON threshold Vcc UV turn OFF threshold Undervoltage quiescent supply current VCC = 10 V SD/OD = 5 V; LIN = 5 V; HIN = 0, CIN = 0 Vcc = 15 V SD/OD = 5 V; LIN = 5 V HIN = 0, CIN = 0 0.5 0.54 Test conditions Min. 1.2 11.5 10 Typ. 1.5 12.0 10.5 450 Max. Unit V V V A
Iqcc
Quiescent current Internal comparator (CIN) reference voltage
3.5
mA
Vref
0.58
mV
Table 9.
Symbol VBS_hys VBS_thON VBS_thOFF IQBSU
Bootstrapped voltage
Parameter VBS UV hysteresis VBS UV turn ON threshold VBS UV turn OFF threshold Undervoltage VBS quiescent current VBS = 10 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 VBS = 15 V SD/OD = 5 V; LIN and HIN = 5 V; CIN = 0 LVG ON Test conditions Min. 1.2 10.6 9.0 Typ. 1.5 11.5 10.0 70 110 Max. Unit V V V A
IQBS RDS(on)
VBS quiescent current Bootstrap driver on resistance
150 120
210
A
Table 10.
Symbol Vil Vih IHINh IHINl ILINl ILINh ISDh
Logic inputs
Parameter Low logic level voltage High logic level voltage HIN logic "1" input bias current HIN logic "0" input bias current LIN logic "0" input bias current LIN logic "1" input bias current SD logic "1" input bias current HIN = 15 V HIN = 0 V LIN = 0 V LIN = 15 V SD = 15 V 120 6 2.2 175 260 1 20 1 300 Test conditions Min. Typ. Max. 0.8 Unit V V A A A A A
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Electrical characteristics Table 10.
Symbol ISDl Dt
STGIPS14K60
Logic inputs (continued)
Parameter SD logic "0" input bias current Dead time Test conditions SD = 0 V see Figure 7 600 Min. Typ. Max. 3 Unit A ns
Table 11.
Symbol Iio Vol td_comp SR
Sense comparator characteristics (VCC = 15 V)
Parameter Input bias current Open drain low level output voltage Comparator delay Slew rate Test conditions VCP+ = 1 V Iod = - 3 mA SD/OD pulled to 5 V through 100 k resistor CL = 180 pF; Rpu = 5 k Min. 90 60 Typ. Max. 3 0.5 130 Unit A V ns V/sec
Table 12.
Truth table
Logic input (VI) Output HIN X H L L H LVG L L L H L HVG L L L L H
Condition SD/OD Shutdown enable half-bridge tri-state Interlocking half-bridge tri-state 0 `'logic state" half-bridge tri-state 1 "logic state" low side direct driving 1 "logic state" high side direct driving L H H H H LIN X L H L H
Note:
X: don't care
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Doc ID 15927 Rev 3
STGIPS14K60
Electrical characteristics
Figure 5.
Maximum IC(RMS) current vs. switching frequency (1)
Figure 6.
(1)
Maximum IC(RMS) current vs. fSINE
1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c.
Doc ID 15927 Rev 3
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Electrical characteristics
STGIPS14K60
3.2
Waveforms definitions
Figure 7. Dead time and interlocking waveforms definitions
LIN
LVG HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE)
INTE RLO CK
CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME
HIN
INTE RLO CKIN G
ING
DTLH gate driver outputs OFF (HALF-BRIDGE TRI-STATE)
DTHL
LIN
CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME
HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL
LIN
CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME
HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL
LIN
CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING
HIN LVG DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) DTHL
(*) HIN and LIN can be connected together and driven by just one control signal
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Doc ID 15927 Rev 3
STGIPS14K60
Smart shutdown function
4
Smart shutdown function
The STGIPS14K60 integrates a comparator for fault sensing purposes. The comparator non-inverting input (CIN) can be connected to an external shunt resistor in order to implement a simple over-current protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leading the halfbridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. The time delay between the fault and the outputs turn-off is no more dependent on the RC values of the external network connected to the shutdown pin. At the same time the internal logic turns on the open drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. Finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external RC network. Figure 8. Smart shutdown timing waveforms
comp Vref
CP+
PROTECTION
HIN/LIN
HVG/LVG
SD/OD
upper threshold lower threshold
1 open drain gate (internal)
2
real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold
TIME CONSTANTS
1 2
= (RON_OD // RSD) CSD = RSD CSD
SHUT DOWN CIRCUIT
VBIAS
RSD
FROM/TO CONTROLLER
SD/OD
SMART SD LOGIC
CSD
RON_OD
Doc ID 15927 Rev 3
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5
14/19
OUT U P T1 D1 U
Figure 9.
Cbu
VBOOT U
LIN SD/OD HIN VCC OUT HVG Vboot
Applications information
LIN-U
Rg
VCC
HIN-U
VCC
Cvcc
DT
Rg
T2 D2 Nu
LVG
Rdt
GND
Cdt
CP+
OUT V
Cbv
VBOOT V T3 D3 V
LIN SD/OD HIN VCC OUT HVG Vboot
GND
Rg
+
VDC
LIN-V
Typical application circuit
HIN-V
Cvcc
DT
M
Rg
T4 D4
Applications information
CONTROLLER
LVG
Rdt
GND
Doc ID 15927 Rev 3
Cdt
CP+
Nv
OUT W
Cbw
LIN SD/OD HIN VCC OUT HVG Vboot
VBOOT W
Rg
T5 D5 W
LIN-W
3.3V/5V Line
HIN-W
Rsd
SD/OD
LVG
Cvcc
CP+ GND
DT
Rg
T6
D6 Nw
Csd
Rdt
Cdt
CIN
R
Rshunt
C
STGIPS14K60
AM05001v1
STGIPS14K60
Applications information
5.1
Recommendations

To prevent the input signals oscillation, the wiring of each input should be as short as possible. By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. Each capacitor should be located as nearby the pins of IPM as possible. Low inductance shunt resistors should be used for phase leg current sensing. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. Additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see Section 4: Smart shutdown function for detailed info). Recommended operating conditions
Value Parameter Supply Voltage Conditions Min. VPN VCC VBS tdead fPWM Applied between P-Nu,Nv,Nw 13.5 Typ. 300 15 Max. 400 18 18 1 20 V V V s kHz Unit
Table 13.
Symbol
Control supply voltage Applied between VCC-GND High side bias voltage Blanking time to prevent Arm-short PWM input signal Applied between VBOOTi-OUTi for i=U,V,W For each input signal -40C < Tc < 100C -40C < Tj < 125C
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Package mechanical data
STGIPS14K60
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 14. SDIP-25L package mechanical data
(mm.) Dim. Min. A A1 A2 A3 B B1 B2 C C1 C2 e e1 e2 e3 F F1 R T 44 0.95 1.2 39 21.6 11.45 24.83 5 6.4 11.1 1.95 3.2 4.3 6.1 0.8 0.3 1.35 0.4 0.55 2.35 3.6 4.7 6.5 1.0 0.5 25.22 Typ. Max. 44.8 1.75 2 39.8 22.4 12.25 25.63 5.8 7.4 12.1 2.75 4 5.1 6.9 1.2 0.7 2.15 0.7
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STGIPS14K60 Figure 10. SDIP-25L package mechanical data
Package mechanical data
8154676 revF
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Revision history
STGIPS14K60
7
Revision history
Table 15.
Date 25-Jun-2009 05-Aug-2009
Document revision history
Revision 1 2 Initial release. Reduced VCE(sat) value on Table 7. Document status promoted from preliminary data to datasheet. Updated package mechanical data, Table 7: Inverter part, Figure 5: Maximum IC(RMS) current vs. switching frequency and Figure 6: Maximum IC(RMS) current vs. fSINE (1). Minor text changes to improve readability. Changes
15-Jun-2010
3
18/19
Doc ID 15927 Rev 3
STGIPS14K60
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Doc ID 15927 Rev 3
19/19

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